Virtual Labs

Electronics and Communication Engineering Digital Logic Design (Logic Gates & Mux-Demux) Experiments

Aim

Theory

Pretest

Procedure

Simulation

Posttest

References

Contributors

Feedback

Aim

Theory

Pretest

Procedure

Simulation

Posttest

References

Contributors

Feedback

Multiplexers using Basic Logic Gates

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Beginner

Intermediate

Advanced

The 2:1 multiplexer using basic logic gates with active low enable input can be build using:

a: Two AND, Two NOT, One OR gates Explanation

Explanation

b: Two AND, One NOT, One OR gates Explanation

Explanation

c: Two AND, Two NOT, Two OR gates Explanation

Explanation

d: One AND, Three NOT, One OR gates Explanation

Explanation

Select the output when S2= S1 = 1 and S0 = 0.

a: Y = 0 Explanation

Explanation

b: Y = 1 Explanation

Explanation

c: Y = D Explanation

Explanation

d: None of these Explanation

Explanation

Identify the circuit shown below.

a: 2:1 Mux Explanation

Explanation

b: 4:1 Mux Explanation

Explanation

c: 6:1 Mux Explanation

Explanation

d: 8:1 Mux Explanation

Explanation

Design, construct and verify a 2:1 Mux using basic logic gates. Get the simulation results evaluated from your faculty.

a: decode input Explanation

Explanation

b: strobe input Explanation

Explanation

c: Select input Explanation

Explanation

d: All of these Explanation

Explanation

Differentiate between multiplexer and encoder?

a: decode input Explanation

Explanation

b: strobe input Explanation

Explanation

c: Select input Explanation

Explanation

d: All of these Explanation

Explanation

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